The present invention relates to a mechanism that ensures the accuracy of measurement data of a signal. More specifically, the present invention relates to performing calibration of trace data that records access to memory.
Trace data (command signal, address signal) of actual access to main memory (DDR DRAM) of the computer can be acquired by using a specialized hardware. DDR DRAM (Double-Data-Rate Dynamic Random Access Memory) is sometimes referred to as DDR SDRAM (Double-Data-Rate Synchronous Dynamic Random Access Memory). DDR DRAM is a type of standard for DRAM including a semiconductor integrated circuit that is used in personal computers.
With DDR DRAM, data is transferred at the rising edge and falling edge of the clock signal, and theoretically, a double data transfer rate is achieved as compared to SDRAM that operates synchronous to the clock. For normal signal integrity checks, calibration is performed by comparing the actual measurement value using a given value such as a test pattern and the like, and an anticipated value. With DDR DRAM, periodic calibration is performed at system startup for the data signal, but calibration is not performed at all for the command signal and the address signal.
Tracing is performed by monitoring a signal line (using FPGA and the like) for the command and address of the measurement target, but if the measurement target is high speed (synchronization at the nanosecond level is required), fine adjustment of strobe timing must be performed or accurate measurement data cannot be obtained. With a trace that uses snoop on the signal line, if calibration is performed by the acquired signal, the calibration operation of the measurement target can also be used for the calibration of the tracer, but adaption of this technique is difficult for the command signal and the address signal of DDR DRAM.
Because there is no technique that calibrates the command signal and the address signal of the DDR memory described above, a mechanism that ensures the accuracy of the measurement data of the tracer is necessary. As a software technique, a specific access pattern is generated in a specific physical address from a CPU, and verification is possible by comparing the measurement data, however several problems exist.
From the fact that concealing access by cache and identification of exact time is difficult, one-to-one correspondence of memory access by SW on the CPU and actual memory access is difficult. Also, with a general purpose OS that uses a virtual address, access to a specific physical address cannot be generated. Synchronization of SW and HW at a high speed nanosecond level is difficult, and detection of verification data from the large amount of trace data is necessary.
With conventional technology that uses a hardware device, a waveform of the DRAM signal can be visualized by sweeping trigger timing and threshold voltage using a logic analyzer. Based on looking at the waveform diagram, fine adjustment of the strobe timing is possible. The logic analyzer displays a signal on a digital circuital that is too fast to be observed by humans. The logic analyzer can only examine the transition timing of the signal, and the measurement value must be examined by a separate protocol analyzer.
However, although existing products that use a logic analyzer as a base are expensive, the amount of data that can be traced is small, and use for long term measurement is not possible. On the other hand, if FPGA is used, a measurement device that is comparatively inexpensive can be implemented, but achieving reliability of a measurement signal similar to that of a logic analyzer that uses a dedicated circuit is difficult. There is demand for a tracer that can ensure reliability of measurement data obtained in large amounts, has general purpose properties, is inexpensive, and has scalability.
International Patent Publication WO2002/063473, Japanese Unexamined Patent Application 2002-229814, and Japanese Unexamined Patent Application 2003-150403 disclose that a required logic function is achieved using FPGA, and a system such as a CPU bus and the like is evaluated (calibrated) using the logic function. Japanese Unexamined Patent Application 2011-59953 discloses a device that verifies logic of the memory controller. However, none of the foregoing publications relate to calibration techniques for a bus that uses the various properties that are a part of memory bus and CPU bus protocol.